PCI-RAD Library

The purpose of this library is to explore the performance of the flight computer on a spacecraft. The flight computer is made of the PCI-RAD, Bridge, OCB, FPGA, boards and other discrete components. This library models the entire system in cycle-accurate detail according to the Enhanced Power PCI document from BAE Systems.

List of library functions:

1. DMA- Single channel
2. Bridge has a buffer of one cache length for each connected device
3. Bridge uses the P60X bus arbitration
4. A single Master can be granted the PCI bus at any time.
5. OCB is a crossbar switch and will immediately send the request. The request can be queued at the destination
6. The Latency Timer is a countdown interrupt. The Master must stop any transaction when the timer expires when it is legal to do so (Spec words). If there are no other requests and the timer expires, the active Master can continue to transact.
7. Cache, memory, processor and DMA parameters are configured for user experiments

There are seven major operations involving the Boards, DDR, CPU and DMA. All operations have Read and Write. There are two levels of arbitration- PCI and Bridge or P60X.  There is a single DDR and all requests from all devices must pass through the Bridge. Each Master has a fragment size that is fixed.  The transaction will be fragmented to this size.  Each fragment is arbitrated separately. The Latency Timer can force the Master to stop the transaction when the timer expires.  The Master must arbitrate to continue transmitting.  The latency timer limits the time a Master gets access to the Bus.

P60X arbitration is ping-pong logic and each device gets two requests before the control is handed over to the other device.

We shall assume all requests including from the Boards and CPU to the DDR are one cache length.  The Memory controller clears the activate signal after each transfer.  Every new request must activate the memory.

Interface Cards connected to the PCI-RAD

Read operation from Board to DDR:

The Board gets access to the PCI based on the priority-arbitration.  Board (EMEM, EIO etc.) sends an address request to the Bridge.  The Bridge gets the data from DDR using the arbitration of the P60X bus.  When the data arrives at the Bridge port, it is read back by the Board.  The Latency Timer restricts the size of each request.

Write operation from Board to DDR:

The Board gets access to the PCI based on the priority-arbitration.  Interface Boards sends an address and the data to the Bridge.  The Bridge sends the data to the DDR using the arbitration of the P60X bus.  The data is first buffered at the Bridge port and when it wins the P60X arbitration, it is sent to the Board.  When the data has been transferred to the Bridge, the PCI bus is cleared and the next request is sent on the PCI.   The Latency Timer restricts the size of each request.

Read or Write operation from CPU to Interface Board (Direct)

CPU sends a read or write request through the P60X bus to the PCI.  When the CPU gets access to the PCI based on the priority-arbitration, it starts transmitting the read address or the write data. If write, it simply releases the bus on completion.  If read, the CPU/Bridge can keep request asserted, and it can get a retry in which case it has to re-arbitrate.

DMA Read or Write Request

CPU to DDR- Read or Write

This request is sent to the P60X bus to the Bridge.  The Bridge uses the P60X bus to select the next request and send it to the DDR. Each request is one cache size.

PCI Arbitration

• 8 Master
• Three levels of priority
• Priority is fixed within a level
• Priority is for the requester
• Requestor can be disabled- Can be dynamic
• Inverse of VisualSim- Level1 is highest and Level 3 is the lowest
• Within each level the priorities are also fixed with the lowest order having the highest priority

Protocol

1. A table is created that has the list of Master’s and their Priority Levels.
2. All the Level 1 devices receive a chance. When all have been given a change, then one device in Level 2 is given a chance.
3. When the single Level 2 has completed, all the Level 1 receives a chance again.
4. The process repeats
5. When all Level 2 have received a chance and all level 1 have received a chance, then one Level 3 gets a chance.
6. This process continues until all level 3 have receives a turn. The process repeats.
7. If the bus is quiet, i.e. there is no requestor, and then the system is reset.
8. If there is only requester, that device has the highest priority.
9. A Requester can be disabled. This means the arriving packet on the port can be dropped.
10. There is a Master queue for read and write. Similarly there is a Slave queue for read and Write.

Delays from the PCI specification: